NCPHA=VALID_TRAILING_EDGE, CPOL=IDLE_LOW, BITS=_8_BIT
Chip Select Register
| CPOL | Clock Polarity 0 (IDLE_LOW): Clock is low when inactive (CPOL=0) 1 (IDLE_HIGH): Clock is high when inactive (CPOL=1) |
| NCPHA | Clock Phase 0 (VALID_TRAILING_EDGE): Data is valid on clock trailing edge (NCPHA=0) 1 (VALID_LEADING_EDGE): Data is valid on clock leading edge (NCPHA=1) |
| CSNAAT | Chip Select Not Active After Transfer (Ignored if CSAAT = 1) |
| CSAAT | Chip Select Active After Transfer |
| BITS | Bits Per Transfer 0 (_8_BIT): 8 bits for transfer 1 (_9_BIT): 9 bits for transfer 2 (_10_BIT): 10 bits for transfer 3 (_11_BIT): 11 bits for transfer 4 (_12_BIT): 12 bits for transfer 5 (_13_BIT): 13 bits for transfer 6 (_14_BIT): 14 bits for transfer 7 (_15_BIT): 15 bits for transfer 8 (_16_BIT): 16 bits for transfer |
| SCBR | Serial Clock Bit Rate |
| DLYBS | Delay Before SPCK |
| DLYBCT | Delay Between Consecutive Transfers |